// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:09 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  asic_in.v
//
//  Common input/override control logic for ASIC-side PHY input lines
//
//  Original Author: Chris Jones
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pma/dig/rtl/asic_in.v $
//    $DateTime: 2014/05/02 08:59:04 $
//    $Revision: #2 $
//
////////////////////////////////////////////////////////////////////////////// 

module dwc_e12mp_phy_x4_ns_asic_in
  #(parameter WIDTH = 1,
    parameter SYNC = 0,
    parameter RST_VAL = 0) (
input  wire [WIDTH-1:0]    asic,
output wire [WIDTH-1:0]    phy,
input  wire                clk,
input  wire                rst,
input  wire                test_ovrd,
input  wire [WIDTH-1:0]    test_ovrd_val,
input  wire                cr_ovrd,
input  wire [WIDTH-1:0]    cr_ovrd_val
);

// Add a sampling input flop on sync interface signals 
wire [WIDTH-1:0] asic_in;
generate
  if (SYNC == 1) begin : sync 
    reg [WIDTH-1:0] asic_sync;
    always @(posedge clk or posedge rst) begin
      if (rst) 
	asic_sync <= RST_VAL;
      else
	asic_sync <= asic;
    end
    assign asic_in = asic_sync;
  end
  else begin : no_sync
    assign asic_in = asic;
  end
endgenerate

// Simple prioritized MUXes to select proper value to send into PHY based on
// mode and control register override pins
//
// hand-instantiate the first mux so that it doesn't get optimized and lose
// test coverage
//
// creg overrides are not intended to meet any timing constraints
//
wire [WIDTH-1:0] asic_creg_val;

dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(WIDTH)) creg_mux (
  .out (asic_creg_val),
  .sel (cr_ovrd),
  .d0  (asic_in),
  .d1  (cr_ovrd_val)
);

dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(WIDTH)) burnin_mux (
  .out (phy),
  .sel (test_ovrd),
  .d0  (asic_creg_val),
  .d1  (test_ovrd_val)
);

endmodule
